Block Diagram

The NanoVNA-H is a sophisticated RF instrument built from surprisingly few components. This page provides a high-level overview of the system architecture and signal flow. Developer-focused pages that follow dive deeper into each subsystem.

System Block Diagram

flowchart TB
  subgraph MCU[STM32 Microcontroller]
      CPU[ARM Cortex-M0/M4]
      I2C[I2C Bus]
      I2S[I2S Interface]
      SPI[SPI Bus]
      USB[USB CDC]
  end

  subgraph RF[RF Signal Chain]
      SI[Si5351<br/>Frequency Synthesizer]
      MIX1[Mixer 1<br/>CH0 Reflection]
      MIX2[Mixer 2<br/>CH1 Transmission]
      BRIDGE[Directional Bridge]
  end

  subgraph AUDIO[Audio Processing]
      CODEC[TLV320AIC3204<br/>Audio Codec]
  end

  subgraph DISPLAY[User Interface]
      LCD[LCD Display<br/>320x240 or 480x320]
      TOUCH[Touch Controller]
  end

  subgraph PORTS[RF Ports]
      P1((Port 1<br/>CH0))
      P2((Port 2<br/>CH1))
  end

  CPU --> I2C
  CPU --> I2S
  CPU --> SPI
  CPU --> USB

  I2C --> SI
  I2C --> CODEC
  I2S --> CODEC

  SI --> |LO| MIX1
  SI --> |LO| MIX2
  SI --> |RF Out| BRIDGE
  BRIDGE --> P1
  BRIDGE --> |Reflected| MIX1
  P2 --> MIX2

  MIX1 --> |IF| CODEC
  MIX2 --> |IF| CODEC

  SPI --> LCD
  I2C --> TOUCH

Hardware Variants

The NanoVNA-H firmware supports two hardware platforms:

Feature	NanoVNA-H (F072)	NanoVNA-H4 (F303)
MCU	STM32F072	STM32F303
Core	Cortex-M0 (48 MHz)	Cortex-M4 (72 MHz)
FPU	None (software float)	Hardware FPU
DSP	No DSP instructions	SIMD DSP instructions
Display	320x240 (ILI9341/ST7789)	480x320 (ST7796S)
Max Points	101	401
RAM	16 KB	40 KB
Flash	128 KB	256 KB

Code Paths

The firmware uses conditional compilation to optimize for each platform. The F303 uses hardware FPU and DSP instructions where the F072 uses software implementations.

Key Components

Si5351 Frequency Synthesizer

Generates RF signals from 600 Hz to 200+ MHz. Uses harmonics for higher frequencies up to 1.5 GHz. Three independent outputs: RF stimulus, LO for CH0, LO for CH1.

NE602/SA612 Mixers

Convert RF signals to audio-frequency IF. The mixer output at ~12 kHz is easily digitized by the audio codec. Two mixers: one for reflection, one for transmission.

TLV320AIC3204 Codec

High-quality stereo audio ADC samples both mixer outputs simultaneously at 192 kHz. Programmable gain amplifiers provide dynamic range control.

STM32 Microcontroller

Runs ChibiOS RTOS, controls all peripherals, performs DSP calculations, drives the display, and handles USB communication.

Signal Flow Overview

Measurement Cycle

For each frequency point in a sweep:

1. Set Frequency: Si5351 generates stimulus (RF out) and LO signals
2. Wait for Settle: PLL needs time to lock (100-5000 us depending on frequency change)
3. Measure CH0: Select CH0 mixer input, accumulate IF samples
4. Measure CH1: Select CH1 mixer input, accumulate IF samples
5. Calculate: DFT extracts magnitude and phase from IF samples
6. Correct: Apply calibration error terms
7. Store: Save S11 and S21 to measurement array

Data Flow

flowchart LR
  A[RF at DUT] --> B[Mixer]
  B --> C[IF Signal<br/>~12 kHz]
  C --> D[Audio ADC<br/>192 kHz]
  D --> E[DSP<br/>DFT]
  E --> F[Complex S-param<br/>Real + Imag]
  F --> G[Calibration<br/>Correction]
  G --> H[Display<br/>Trace Data]

Memory Map

Flash Storage

Region	F072 Address	F303 Address	Contents
Firmware	0x08000000	0x08000000	Application code
Cal Slot 0	End of code	End of code	Calibration data
Cal Slot 1-4	+0x1800 each	+0x4000 each	Additional cal sets
Config	After cal slots	After cal slots	System configuration

RAM Usage

// Key data structures in RAM
float measured[2][SWEEP_POINTS_MAX][2];  // Measurement results
float cal_data[CAL_TYPE_COUNT][SWEEP_POINTS_MAX][2];  // Calibration data
pixel_t spi_buffer[SPI_BUFFER_SIZE];     // LCD/SPI buffer
audio_sample_t rx_buffer[AUDIO_BUFFER_LEN * 2];  // DMA audio buffer

Peripheral Configuration

I2C Bus (400-900 kHz)

Connected devices:

• Si5351 frequency synthesizer (address 0x60)
• TLV320AIC3204 audio codec (address 0x18)
• Touch controller (on some displays)

I2S Interface (192 kHz)

• Stereo audio from TLV320AIC3204
• DMA transfer to rx_buffer
• Half-transfer and complete interrupts trigger DSP

SPI Bus (High Speed)

• LCD display data
• Optional SD card (on H4)
• DMA for bulk transfers

USB (Full Speed)

• CDC (Virtual COM Port) for shell commands
• Supports NanoVNA-Saver and other PC software

Clock Architecture

flowchart LR
  XTAL[26 MHz TCXO] --> SI[Si5351]
  SI --> |CLKIN| CODEC[TLV320AIC3204]
  HSE[8 MHz HSE] --> PLL[STM32 PLL]
  PLL --> |48/72 MHz| CPU[System Clock]

The Si5351’s 26 MHz TCXO provides both the RF reference and the audio codec clock, ensuring they remain phase-coherent.

Power Architecture

• USB Power: 5V from USB connector
• 3.3V Rail: LDO regulator for digital circuits
• Battery: Optional LiPo with charging circuit (H4)
• LCD Backlight: PWM-controlled brightness

Power Consumption

Typical current draw is 100-150 mA during sweep, dropping to ~50 mA when idle. Battery life on the H4 is approximately 2-3 hours of continuous use.

Next Steps

Dive deeper into specific subsystems:

• Signal Pipeline - Audio processing and gamma calculation
• Frequency Synthesis - Si5351 PLL operation
• Harmonic Mixing - Coverage above 300 MHz
• Threading Model - RTOS task structure
• Display Pipeline - Efficient screen rendering